This invention is in the field of integrated circuit fabrication, and is more specifically directed to the fabrication of integrated circuits according to complementary-metal-oxide-semiconductor (CMOS) technology.
The use of complementary-metal-oxide-semiconductor (CMOS) integrated circuit technology has become widespread over recent years, due to the significant improvements in speed-power product provided by this technology. As is fundamental in the art, CMOS integrated circuits include metal-oxide-semiconductor (MOS) transistors of both p-channel and n-channel types within each basic logic building block, by way of which digital logic operations may be carried out at relatively high switching speeds and extremely low static power dissipation. A well-known extension of CMOS technology is bipolar-CMOS (BiCMOS) technology, in which bipolar transistors are integrated with the p-channel and n-channel MOS transistors to provide even higher switching speeds and high-power drive characteristics.
However, the presence of both p-channel and n-channel transistors in the same integrated circuit increases the complexity of the manufacturing process of CMOS devices, from that required to fabricate integrated circuit devices that have only n-channel or p-channel devices. Fundamentally, each doping step performed for a single channel type device must be repeated for the opposite channel type device. These doping steps include not only the doping of source/drain regions for the MOS devices, but also the doping of both n-type and p-type wells, or tanks, into which the transistors (p-channel and n-channel, respectively) are formed, and additionally, in the case of polysilicon gate devices, the doping of both n-type and p-type polysilicon gate electrodes.
Source/drain doping operations are conventionally carried out by way of ion implantation, for each conductivity type, followed by high temperature annealing, as is well known in the art. In conventional CMOS processes, the source/drain implants are masked so that the implant of one conductivity type does not counterdope the source/drain regions of transistors of the opposite conductivity type. Referring now to FIGS. 1a through 1e, an example of a conventional CMOS process will now be described to illustrate the complex masking that is typically performed.
FIG. 1a is a cross-sectional view of an integrated circuit that has been partially fabricated according to a conventional CMOS process. At this point in the process, substrate 2, which is typically a very lightly-doped (p-type) body of single crystal silicon in wafer form, has wells 4, 6 formed at its surface. P-type well 4 is a lightly-doped p-type region of substrate 2, while n-type well 6 is a lightly-doped n-type region of substrate 2. Field oxide structures 5 have also been formed at the surface of substrate 2, for example by way of local oxidation of silicon (LOCOS), and serve as isolation structures for active source/drain regions that will subsequently be formed. Gate dielectric 7 overlies those portions of the surface of wells 4, 6 that are not occupied by field oxide structures 5; gate dielectric 7 is typically formed of thermal silicon dioxide (grown from substrate 2), deposited silicon dioxide or silicon nitride, or a combination thereof. Also at the point of this conventional process that is illustrated in FIG. 1a, gate structures 8n, 8p are in place at selected locations of wells 4, 6, respectively, separated therefrom by gate dielectric 7. Gate structures 8n, 8p may be formed according to any one of a number of different approaches that are known in the art. For example, gate structures 8n, 8p may be formed of doped polycrystalline silicon (n-type and p-type, respectively), of a refractory metal (e.g., tungsten) or metal silicide (e.g., tungsten disilicide), or of a combination of materials, such combinations also being known in the art. In addition, additional processing such as channel stop implants (under field oxide structures 5) and threshold voltage adjust implants will typically have been performed at the state of manufacture illustrated in FIG. 1a. For example, threshold voltage adjust implants are typically performed into the active regions of wells 4, 6 (i.e., those regions at which field oxide structures 5 are not present), prior to the formation of gate structures 8.
In this conventional process, as is now standard for modern MOS processing, n-channel transistors will be formed into well 4 so as to have a graded junction, also referred to as "lightly-doped drain" junction. According to this approach, the source/drain regions for n-channel transistors are formed so as to be relatively lightly-doped and shallow at locations directly adjacent to the gate, and more heavily-doped and deeper at locations spaced away from the gate. This construction is preferred for n-channel transistors to prevent the occurrence of "hot carrier effects" that can deleteriously change the operating parameters of the transistor over time.
Referring now to FIG. 1b, photoresist 10 is illustrated as in place over those portions of well 6 at which p-channel MOS transistors are to be formed. Photoresist 10 is formed by conventional deposition and spinning of photoresist to a thickness sufficient to stop ions in the subsequent implant operation from penetrating therethrough; masking, patterning, and developing of the photoresist 10 is then performed to define the locations at which photoresist 10 is to remain. As illustrated in FIG. 1b, the structure is then subjected to a phosphorous ion implant, at a dose and energy selected to provide the lightly-doped drain extensions of the source/drain regions, for prevention of hot carrier effects as noted above. This implant is commonly referred to as the "reach-through" implant. As a result of this implant, well 4 has phosphorous ions located in a thin layer near its surface at those locations not masked by field oxide structures 5, photoresist 10, or gate structure 8n.
FIG. 1c illustrates the structure after removal of photoresist 10 from the surface of the integrated circuit, including from over well 6. Sidewall dielectric filaments 11 are then formed along the sides of gate structures 8n, 8p, by the deposition of a conformal silicon dioxide or silicon nitride layer, followed by an anistropic etch to remove the deposited dielectric from the planar surfaces of the structure, leaving filaments 11 as illustrated in FIG. 1c. Sidewall filaments 11 serve to define the location at which the heavy source/drain implants are spaced away from the gate electrode, particularly in the case of the n-channel transistor formed in p-well 4, as n-channel devices are particularly susceptible to hot electron effects. As in this example, lightly-doped drain extensions are not necessary for p-channel devices, as the lower mobility of holes renders p-channel devices much less susceptible to hot carrier effects.
The n-type source/drain implant is next performed, as illustrated in FIG. 1d. As in the case of the lightly-doped drain implant, photoresist 12 is applied and patterned so as to protect n-well 6 (at which the p-channel transistors will be formed) from the n.sup.+ source/drain implant, which is typically performed with a relatively heavy dose and energy. The n-type source/drain implant species may be phosphorous or arsenic; alternatively, an implant of each of both species may be performed, as illustrated in FIG. 1d, depending upon the particular junction profile desired.
Conventional CMOS processing then continues with the formation of the p-type source/drain regions by way of a masked ion implantation. As shown in FIG. 1e, photoresist 14 is applied over the surface of the integrated circuit structure, and is patterned to protect the surface of p-well 4 (at which the n-channel transistors are formed) from the p-type implant. Ion implantation of the p-type species, typically boron, is then performed, at a relatively heavy dose.
Following the masked implants described hereinabove relative to FIGS. 1a through 1e, photoresist 14 is removed, and the structure is subjected to a high-temperature anneal to drive-in the implanted dopant and form the source/drain junctions. Conventional anneals include furnace anneals, and also rapid thermal anneal (RTA) by way of which the wafer is subjected to an extremely high temperature anneal for a brief period.
As is evident from the foregoing description of the conventional process, multiple photolithographic operations are required to pattern the various implants. Especially as the desired critical dimensions of transistors continue to shrink within the submicron regime, for example to on the order of 0.25 .mu., the cost associated with each photolithography operation continues to increase. Elimination of photolithographic operations from the process is therefore desirable to reduce manufacturing cost.
By way of further background, the diffusion of dopant from doped silicon dioxide layers into adjacent silicon semiconductor material is a well-known phenomenon in the art. In this regard, the inclusion of barrier layers (e.g., undoped silicon dioxide, or other materials) between doped silicon dioxide and the silicon bulk has been proposed to prevent such diffusion.